A Low Overhead Fault-tolerance System Of Reconfigurable Based On FPGA

Because circuit design based on FPGA is highly flexible and efficient, the application of FPGA becomes more and more extensive. SRAM-based FPGA has many advantages including high-performance, high-density, low-cost and programmable. These make that circuit designed by FPGA can effectively reduce the cycle and cost of design, as well as can modify the design in orbit. FPGA is highly favored by designers of space applications. But due to its structural characteristics, FPGA is affected easier by external factors(such as radiation, high-energy particle bombardment), which results in bit upset, functional errors and even breakdown. If we do not take certain methods to reinforce the FPGA circuit, its reliability will not be guaranteed in space applications. Because the conditions of space environment are very harsh. Failures may bring disastrous effect which happen in FPGA. The application of FPGA dynamic reconfigurable function provides a solution in improving the reliability of FPGA circuit design.Currently, dynamic reconfigurable technology of FPGA has become increasingly mature, and it is important to design high reliability of fault-tolerant system based on FPGA. The fault-tolerance and reinforcement must bring additional hardware overhead and time cost. In order to reduce the cost of the system and keep continuity when system is working, the hardware overhead and time cost of the entire fault-tolerant system should be reduced as much as possible, under the premise of reliability. A low overhead fault-tolerance system is proposed,based on reconfigurable technology of FPGA. The main work of the dissertation concludes as following:(1)The reason and harm of errors occurred in FPGA are analyzed, and the relevant common fault tolerant and reinforcement technology are clarified.(2)Based on previous researches, a low overhead fault-tolerance system is proposed. Circuit is reinforced by DWC(Duplication With Comparison), faults are located by verifying the configuration bits, and circuit is repaired by reconfiguration.(3)The hardware overhead of system is calculated though inplementing circuit, and a comparison is made with other fault tolerance system. The hardware overhead of the system is further reduced about 140slices, based on keeping reliability and relatively low time cost.