High-Speed SERDES Interface Modeling And The Design Of PLL

With the development of communication technology, parallel transmission is difficult to meet the bandwidth and power consumption requirements. Because of the advantages of high transmission speed, low power consumption and strong anti-interference ability, serial transmission become the mainstream way of transmission. SERDES interface can realizes the function that convert between the parallel and the serial, so it became the mainstream transport interface. Among them,8B/10B SERDES which has DC balance and ease of advantages such as AC-coupled, becomes the focus of study on interface circuit.This paper describes the four implementations of SERDES architecture, and in accordance with their respective advantages and disadvantages, selected 8B/10B SERDES as the object of study, Detailed analysis and principle of SERDES modules in the system is introduced, which includes parallel-series conversion circuit, half-rate clock selecting circuit, duty cycle 1:5 of five-frequency circuit and series-parallel conversion circuit. According to the sending, and receiving channels, a Simulink model of the system is building. When the clock frequency of parallel signal is 250MHz, the frequency of output signal can reach 2.5Gbps.Charge-pump phase-locked loop (CPPLL) as a important part of 8B/10B SERDES, clocks for the entire system, its performance will be directly affecting the transmission accuracy. This paper component in a CPPLL based on the theory and analysis of non-ideal factors, and circuit design of this thesis are presented with non-ideal solutions. Finally, a 1.2/2.5V power supply voltage, using SMIC 65nm CMOS technology, simulation and analysis of the CPPLL. The simulation results that, when the input signal frequency is 100MHz, CPPLL stable 2.5GHz output clock signal, locking time only 0.6us, meets the SERDES system performance requirements for CPPLL.