The Design And Implementation Of Emission Subsystem Of The High-Speed Bit-Error-Rate Instrument

The code-error testing instrument need to be improved with the data-rate becoming faster, so the high-speed code-error testing instrument is designed aiming at the scheme of "the integrated terminal-processing technology of earth station"system, which data-rate reaches 300Mb/sc It'not only can provide an important evaluating metewand for the improvement of this system, but also can be applied to the other high-speed communication system. The mission of the project is to design and realize the emission subsystem of the code-error testing instrument. The FPGA and Parallel-to-Serial convert technique offer a way to resolve this problem.On basic of researching the principle of high-speed Parallel-to-Serial convert, appling the FPGA technology to the high-speed circuit design, this paper designs a scheme to realize the high-speed signal generation using the high performance Parallel-to-Serial convert chips and the FPGA-it's core control chip. Not only the visualized circuit structure but also the problems in the debugging and the measure to solve them is given in this paper. The emission subsystem arrives the expectant performence in the system debugging.