Design And Implementation Of High Performance Wireless Communication DSP With VLSI Based On Stochastic Computation

With the development of information technology, people rely on more data service than ever before. Humans will step in the ‘Big Data Era’ in the near future. As one of the core technologies of ‘Big Data Era’, wireless communication system, faces a critical challenge on the rapid growth of data service. The complexity of wireless communication system increases dramatically for the requirement of transition more data on limited spectrum resource in the future. The evolution of wireless communication challenges the Very Large Scale Integration(VLSI) implementation of Digital Signal Processing(DSP) with high speed, high complexity and high power consumption. Especially, the topic of design and implementation of high complexity wireless communication in green communication system is challengeable, valuable and requirable.In this dissertation, the main research object is the methodology of wireless baseband signal processing and design. A low complexity and low power VLSI implementation of wireless DSP is proposed based on stochastic computation, which includes elemental arithmetic units, basic signal processing modules, channel decoders and Multiple-in-Multiple-out(MIMO) detectors. The contributions of the dissertation are summarized as follows.1. The high performance elemental arithmetic unit based on stochastic computation is investigated. The proposed stochastic arithmetic unit can reduce the computation latency in an exponent time as traditional stochastic computation. It also achieves the same accuracy as traditional Two’s Complement System(TCS) but much lower hardware cost only 10% as traditional.2. The basic signal processing modules in wireless communication are designed and implemented by proposed arithmetic units. With ultra simple logic structure, the serial FIR filter is implemented by a single multiplexer; while no logic gates is required in the parallel FIR filter but with wire selections. The parallel Fast Fourier Transform(FFT) is designed with high performance arithmetic units, which achieve three times hardware efficiency improving.3. A fully parallel Turbo decoder is proposed with sufficient theoretic study and analysis. As a known fact, the traditional turbo decoding is a sequential processing, which is unable to be implemented as a fully parallel form as LDPC decoder. Due to a novel decoding strategy adopted in fully parallel Turbo decoder, the mathematical model is established to analyze the state metric and extrinsic information updating behavior. According to the dynamic behavior study and BER simulation, the parallel decoder can achieve an ultra high decoding speed without performance loss. Moreover, the new analysis method can be used as the design guidelines for the implementation based on stochastic computation. A new fast termination method is also provided for stochastic Turbo decoder according to the proposed guidelines. To reduce the complexity of fully parallel decoder, the stochastic computation technology is employed to design high performance stochastic decoder. According to the design report, the hardware efficiency of proposed decoder is nearly twice as traditional turbo decoder. An optimization method is also proposed for the stochastic LDPC decoder.4. In the dissertation, a stochastic computing framework for a Markov Chain Monte Carlo(MCMC) Multiple-Input Multiple-Output(MIMO) detector is proposed, in which the arithmetic operations are implemented by simple logic structures. Specifically, we introduce two new techniques, namely a Sliding Window Generator(SWG) and a Log-likelihood ratio based Updating Method(LUM), to achieve an efficient design. The SWG utilizes the variance in stochastic computations to increase the transition probability of the MCMC detector, while the LUM reduces the hardware cost. As a case study, we design a fully-parallel stochastic MCMC detector for a 4×4 16-QAM MIMO system using a 130 nm CMOS technology. The proposed detector achieves a throughput of 1.5 Gbps with only a 0.2 dB performance loss compared to a traditional floating-point detection method. Our design has a 30% better ratio of gate count to scaled throughput compared to other recent MIMO detectors. The core arithmetic unit of Minimal Mean Square Estimation(MMSE) MIMO detector, matrix multiplication and matrix inversion, are implemented by high performance stochastic arithmetic logics. The proposed MMSE MIMO detector has higher hardware efficiency than traditional method. To improve the detection performance The Gibbs sampler of the MCMC detector in SIM is updated by the decoded bits from a channel decoder directly. In a general scope, the channel decoder is part of the updating unit to generate new samples in the MCMC updating process. We also implement the SIM in a fully parallel scheme, which matches the I/O rule of the stochastic decoder to avoid complex conversion and addressing operation.The hardware efficiency is improved 55% above. The proposed MIMO detector has a promising performance for the future iterative processing system.