Design And Implementation Of Stochastic Computing-Based LDPC Decoder

LDPC codes are an important class of linear block error correcting codes, which can provide decoding performance close to the Shannon limit and have been adopted by several standards such as deep space communications, satellite communications, and wireless local area networks. Nowadays, LDPC codes has become one of the channel encoding candidates for next-generation wireless communication system. Due to the lack of low cost and high performance decoding algorithm,LDPC codes didn't arise extensive attention in the early period. With the presentation and development of iterative decoding algorithm, the complexity of LDPC decoding algorithm was gradually reduced, but its hardware implementation complexity was still high.While the implementation complexity of LDPC decoder can no longer be reduced significantly by the traditional binary numerical representation and computing system,the stochastic LDPC decoding was proposed. The hardware implementation complexity of LDPC decoder is efficiently reduced by using novel stochastic numerical representation and computing system. However, hold state (HS) problem of variable nodes (VN) is still existing in stochastic LDPC decoders, which seriously restrains the decoding performance. Meanwhile, existing stochastic decoding algorithm has slightly performance loss compared with traditional algorithm. Therefore, there are still a lot of problems to be studied and solved for the application and implementation of stochastic LDPC decoder.This dissertation focuses on the design and implementation of performance improvement strategy for stochastic LDPC decoder. The most important contribution of this study is the application of the packet coding method in stochastic LDPC decoding.The contents of this dissertation are as follows. The basic principle of stochastic computing and logical computation on stochastic bit stream with linear finite-state machines are presented, in addition, analysis and simulation are given. Then, the principle of LDPC codes and the improvement processing of decoding algorithm are reviewed.Moreover, typical stochastic LDPC decoding algorithms are discussed. The whole decoding algorithm framework is shown immediately after the re-randomization units,including EM, TFM and MTFM, which were used to settle the HS problem of VN, are described in details. A novel dual channel updating EM method is proposed to improve the decoding performance. After that, packet coding technology is first applied in stochastic LDPC decoder. The implementation structure of stochastic LDPC decoder is designed and the RTL codes for four code rates stochastic LDPC decoders are written and tested. The decoding performance of designed stochastic LDPC decoders are verified by co-simulation of Simulink and Modelsim.The main works and contributions of the dissertation are summarized as follows:(1) A novel dual channel of variable nodes and check nodes updating EM method is proposed to release the VN from HS, which can achieve better decoding performance than one channel method.(2) Packet coding technology is first applied in stochastic LDPC decoding which improves decoding performance significantly and retains short decoding delay and low complexity.(3) The bit error ratio and the block error ratio performance of proposed stochastic LDPC decoding algorithm was analyzed and depicted on the MATLAB software platform. Then, the function and performance verification of the RTL codes of the stochastic LDPC decoder are carried out by using Simulink and Modelsim co-simulation.