| As Complementary Metal Oxide Semiconductor (CMOS) channel lengths shrink continuously in order to improve performance and packing density, lithography and short channel effects have proved to be major limitations. Recently vertical MOSFETS (VMOS), also known as surround-gate transistors, or 3-D side-wall transistors have been shown to overcome these process limitations. In this work we present novel deep submicron vertical SiGe/Si PMOSFETs and NMOSFETs fabricated by Ge implantation and UHVCVD growth. Germanium implanted in the Si vertical channel forms strained SiGe layer which increases the drive current in P-channel devices. PMOS drive current can be increased by about 100% compared to Si control devices. Thus, this technology offers CMOS circuit designers the flexibility to match PMOS and NMOS current drive capabilities, which was previously limited by the difference in electron and hole mobility in Si. We also present data that shows that the drive current of vertical strained SiGe NMOSFET is higher compared to well control Si vertical NMOSFET. We have studied for the first time a novel side-wall strained-Si device without relaxed SiGe buffer layers in this work. The electrical C-V data indicates that a band offset is formed in the novel devices. TEM pictures show a high quality crystalline tensile-strained-Si layer can be grown on the side-wall of a compressively strained SiGe layer. In addition to device results, the theoretical sidewall conduction and valence band offset calculations, relative to strained SiGe layer, are also presented in this work. |
