10G BASE-T LDPC Decoding Hardware Implementation And Software Verification

Low Density Check code(LDPC, Low Density Parity Check- Codes) is a kind of can close to Shannon limit of gradual good code, its long code performance even more than the Turbo Codes. Due to the low density check code with low decoding complexity, low error flat layer many advantages, its good application prospect in the reliable information transmission has drawn attention of the IT industry and academia, became the most popular in the world of error control coding of one of the hot research topic. But the encoding complexity and decoding complexity is higher, to a certain extent restricts the application of design a suitable for on-chip system available on the encoder and decoder for many scientific and technical workers and engineers to the direction and goals.In this paper, it is working in this direction, on a piece of system implementation, silicon area, power consumption, performance, frequency, encoding throughput, decoding throughput to achieve a reasonable balance. In theory analysis of LDPC general information sequence and generator matrix multiplication directly, RU matrix coding method, analysis IEEE10 G base-t LDPC code used in this specification method in the construction of the put forward their own solutions, designed a reduce the size of the encoder; Confidence propagation algorithm is analyzed theoretically, and the algorithm of the minimum and algorithm, in terms of the decoder architecture, analyzes the layered, pipelining architecture, assembly line throughput problems in architecture. In the study on the previous work of progress at the same time, deep understanding of the problems, put forward their own solutions and hardware implementation method. The main content as follows:1. According to the IEEE used in 10 base-t g LDPC code generator matrix and the check digit in the part of the generation of the vector, about half is very sparse features, storage so many zero is not necessary, proposed using the vector counter, counter information sequence to generate the bit-stream generated vector solution, decrease the hardware resources needed for the code.2. In view of the LDPC codes in the decoder bit channel information range is too big and too small, decoding performance degradation problems, puts forward the solution of the pretreatment method, adjust the size of the bit channel information by equilibrium to give full play to the scope of the decoder performance; By adding the offset, move a bit channel information to a reasonable range.3. In view of the decoder work, update and check variable node updates the problem of large amount of calculation, pipeline architecture was proposed to satisfy the back-end synthesis frequency pressure, in the architectural design phase IP when use problem to think ahead, to improve the frequency of the decoder can be integrated.