Ldpc Encoder And Decoder Based On The Cmmb-of Stimi Standard, Design And Realization

LDPC (Low Density Parity Check) code is kind of channel code algorithm with the performance of the most close to the Shannon limit. With the development of LDPC algorithm which has a hardware-friendly trend, the VLSI realization of LDPC decoder is becoming ever the focus of researchers.The formal version of Mobile Multimedia Broadcasting specification of China was published in 2006. This specification is applied for the satellite-terrestrial interactive multi-service infrastructure. It is referred as STiMi. STiMi is a technique specification for the mobile multimedia broadcasting. In order to meet the requirements multimedia service in the wireless environments LDPC codes, the FEC code scheme close to Shannon limitation, is adopted in STiMi.Based on the highly structured feature of LDPC code in CMMB-STiMi standard, we proposed the hardware structure and implement of LDPC decoder and encoder with high speed up to 100 MHz. The decoder employs the normalized BP-Based decode algorithm, and partially-parallel structure for regular LDPC code in CMMB-STiMi standard. With the special approach of data storage which decreases the complexity of control logic and reduces the requirement for memory, the decoder can realize simultaneous the writing and reading of huge amount of data. We use two schemes of the FPGA implement of our design which use Virtex-II XC2V6000 and Virtex-4 XC4VLX80 from Xilinx, and GMAP integrated circuit board as hardware platform. According to our test of performance, under the AWGN channel and BPSK modular, when the code rate is 1/2, and the signal-to-noise ratio is 1.8 dB, the error of bit has already been below 10? 4; the signal-to-noise ratio is 1.8 dB, the error of bit is below10?6 . Compared to the result of simulation under ideal situation, the performance of the LDPC decoder has just 0.1dB distance for rate of 1/2 and 0.3dB for rate of 3/4.