Study Of Device Characteristics And Design On Gate-enclosed NMOS Transistors

With the rapid development of semiconductor technology and the decrease of device process geometries, CMOS IC reliability issues become increasingly significant. Especially in the aerospace industry, reliability issues caused by radiation is particularly prominent. Radiation hardening increasingly high demand for the product,the ability of anti-radiation chip and system requirements are also increasing. In many radiation hardening method, A gate-enclosed transistor is designed layout for a total ionizing dose radiation effects is an effective radiation hardening method. Then, How to use the correct aspect ratio extraction method for the gate-enclosed design, and to estimate their impact on the area of loss, reliability study of the gate-enclosed NMOS transistors become the reliability of the semiconductor device research stage hotspots. Based on the above background, the paper focuses on design and device characterization of a gate-enclosed NMOS transistor carried out research. Specific studies are as follows:Based on the commercial CMOS process line, we designed and fabricated a gate-enclosed NMOS transistor with different thicknesses gate oxide layers and different gate structures, mainly including annular-gate, ring-gate and the stripe-gate, that for the comparative study. And to study the transfer and output characteristic curve of the prepared various samples, the results show that the designed NMOS transistor meet the design requirements. And studied the minimum width to length ratio, the transistor layout area of the annular-gate, ring-gate and stripe-gate of the NMOS transistor, and comparative Studied three method extracting effective W/L of gate-enclosed NMOS transistor, experiments show midline approximation method of annular-gate used commonly and mean method of ring-gate used to extract the effective W / L caused by errors are within the acceptable range.Through for the different gate oxide thickness of gate-enclosed NMOS transistor computer simulation study and radiation experiments study. By adjusting the process fix parameters, making the experimental data and simulation results reache a good consistency. The simulation and experimental results show process line of In the thinner gate oxide, anti-TID ability better for a gate-enclosed NMOS, strengthening effect of the ring-gate after the annular- gate.Comparative study hot carrier effects of the ring gate, annular-gate and stripe-gate NMOS transistor NMOS transistor based on the 0.18 um CMOS process, through its electrical characteristics before and after stress comparative analysis, with the accumulation of DC stress degradation time, NMOS transistor leakage current will be reduced, the threshold voltage increases, transconductance peak is also reduced. Also, the same width to length ratio of NMOS, annular gate most degraded, followed by ring-gate with stripe gate less. Therefore, although the gate-enclosed NMOS transistor can well improve the ability of anti-TID, but for the anti-HCI effect no advantage.