The Design Of Anti-Radiation Of IC Module

Recently years, it is becoming one of the important topics to study the effects and mechanisms of ionizing radiation for semiconductor devices and integrated circuits and to improve their radiation hardening in microelectronics field. Radiation hardening electronics has been become a comprehensive marginal subject and making full use of important action. The radiation environment of outer space is capable of effecting CMOS devices in three ways. The first, termed total does, is accumulated ionizing radiation effects. Two other effects are transient phenomenon called Single Event Upset (SEU) and Single Event Latchup (SEL).The total dose radiation effects of MOS structures and their investigation are reviewed and discussed in this dissertation .The well known theory for the characterization of both oxide and interface trap charges is also discussed. The effects of SiO2 /Si charges on the threshold voltage of four terminal MOSFET structures under high field stress were studied and some interesting results have been obtained. It is a qualitative method to estimate effects of high total dose radiation for MOS device. According to the rule of SiO2 /Si charge changes with radiation, a total dose hardness design has been proposed for simple CMOS logic circuits and its SPICE simulation results were presented that with this method, under the conditions of radiation-induced NMOS and PMOS threshold voltage drift 0.15V and 0.1V, the noise tolerance of the circuit controls the basic unaffected. CMOS inverter, NOR, and NAND are the basic units of a CMOS digital circuit, for resisting total dose radiation-hardened to CMOS digital circuit, the key is to CMOS inverter, NOR, NAND resistance to a total dose of radiation-hardened circuit design.This paper introduces the cause of radiation and single event upset and the harm of radiation to CMOS digital circuit and the harm of single event upset to SRAM are discussed especially. The hardening techniques in circuit design such as assistant circuit and redundancy circuit for anti-SEU reinforcement are proposed, and based on it we study anti-SEU Circuit Design of the D flip-flop, and also EDA tools SPICE is used to finish simulation test.