Research On The Technology Of Carrier Synchronization In FPGA For GNSS Signal

In recent years, with the rapid development of Satellite Communications, Satellite Positioning, Telemetry and Tele-control, the technology of carrier synchronization is favored by more and more researchers, and has obtained a breakthrough. In the National Support Program "The key technology and system development of AIS/GNSS marine navigation equipment (2012BAH36B02)", a universal PLL is needed for carrier extraction at the receiving end of the equipment. For an example, it needs direct extraction method to acquire carrier in the double sideband suppressed carrier modulation. There are two kinds of direct extraction methods, square loop and costas loop. There is a restriction cannot be neglected for square loop that the whole loop have to work on the carrier of the second harmonic generation. When the carrier frequency is very high, it will greatly increase the cost. Therefore, this paper will mainly study the costas loop to extract carrier.As an application of PLL (Phase-Locked Loop), costas loop plays a great role in the actual carrier synchronization. Firstly, this paper makes an in-depth research for PLL, mainly including its composition, working principle and basic performance. Then it concretely studies the implementation of costas loop, and makes a structural division for the loop. It is mainly divided into three modules, namely phase detector module, loop filter module and DDS module, they are also the main components of PLL. In the realization of phase detector, it is divided into another two sub-modules, multiplier module and FIR digital low-pass filter module. Finally, it design and implement each module.This paper uses Verilog HDL hardware description language to program all the modules, and will be performed on the ISE hardware development platform which belongs to the XILINX company. Simulation software is associated with Modelsim se 6.5. If the simulation of each module reaches the expected goal, it will begin the simulation of the top module. At last, it will use the virtex4 development board to verify the whole program, and the final results will be displayed on the oscilloscope.