Research On Synchronization Technology Of Spread Spectrum Receiver

Spread spectrum communications has a very important position in the field ofcommunication, because of its excellent ability of resisting jamming, multiple access,resisting multipath fading etc, which has been widely used in military and civiliancommunications. With the rapid development of communication technology, high-speeddynamic wireless communication has become the inevitable trend of development ofcommunication, which requires newer and higher performance in the spread spectrumcommunication system, and also makes the design of the spread spectrum receiversystem more stringent. Synchronization technology as a core technology in the digitalspread spectrum receiver, that the synchronization’s performance is good or bad willdirectly affect the overall system’s performance. Therefore, the research ofsynchronization technology, especially the optimization of the synchronizationperformance, has great practical value in the spread spectrum communication.The subject from the research of digital spread spectrum receiver,focusing on theoptimization design of synchronization performance in spread spectrum receiver, andthrough the methods of Matlab emulation and FPGA hardware verification to prove thefeasibility of the design.The paper first analyzes the background and the present research status ofsynchronization technology in direct sequence spread spectrum communication,researches the matched filter PN code synchronization algorithm based on deepunderstanding of the basic principles of direct sequence spread spectrum systems andsynchronization theory. Compares the traditional sliding correlation algorithm and thematched filter algorithm, then select a faster capturing pseudo-code of matched filteralgorithm, and design optimized matched filter to save resources programs during thedesign of the pseudo-code synchronization system. Use Matlab to Model and simulatethe designed program, and use hardware description language to design and implementthe matched filter pseudo-code synchronization system.Secondly, focus on carrier synchronization based on the digital Costas loop, detailanalysis and describe the design and the parameter settings of each module such asnumerical control oscillator, low pass filter, loop filter etc in the digital Costas loop. Usethe methods of adjust the structure of low-pass filter and cut-digit of each module’sinput and output to optimize the overall design of the Costas loop in the design process, saving resources occupancy rate. Simulate the digital Costas loop carriersynchronization system’s performance by MATLAB/Simulink, program and implementit in ISE environment.Finally, design and make hardware verification platform, which take the XilinxSpartan3XC3s2000FPGA chip as the core, download the designed program to thehardware platform to verify, test results show that the design of PN codesynchronization and carrier synchronization system meets the system designrequirements to realize the dispreading and demodulation of receiving signal, which hasa guiding role in the practical application.