Research And Implementation Of A DSP Event Manager IP Core

With the rapid development of microelectronics technology and computer science, digital signal processor(DSP) has been widely used in many different fields,including: power electronics, image processing, computer networks, wireless communication, smart home, etc. Commercial DSP performance is becoming better and better and the cost is getting lower and lower because of the improvement of IC manufacturing technology and chip design technology and the increasingly powerful of electronic design automation software. The characteristics of high cost-effective expand the application areas of digital signal processor, especially the excellent real-time processing ability in the embedded application, so DSP has an irreplaceable position in the market.DSP is widely used in embedded applications of the high real-time requirement such as motor control. In these applications, real-time processing performance of the DSP on the one hand is reflected in the frequency of the DSP core and the data throughput, so which requires a higher clock rate, more parallel processing units,wider data bus and larger data storage space in the DSP; on the other hand, reflected in the hardware accelerated approach to enhance the ability of signal processing.Compared with the software, hardware accelerated approach can significantly improve the real-time processing capability. What’s more, this approach can improve performance as much as 10 times.The purpose of this study is to develop an "event manager IP", used in the DSP processor, which can implement the DSP processor real-time control and management for the motor system by hard ware acceleration. The strength of the peripheral module performance will directly affect the precision and speed of motor drive circuit system.According to the project on the "event manager IP" functions and technical requirements, firstly, the task is finished, which includes the system IP design principles, the system modeling and simulation, the function module division and the port signal definition. The "event manager IP" is divided into several important modules, including: general timer module, dedicated compare PWM module,quadrature decoding module, dead-cell module, data acquisition module, interrupt system, etc. Secondly, RTL code compilation and simulation of each module are completed. Finally, all module are integrated to achieve the design of "IP event manager". System simulation of "event manager IP" is accomplished from thefollowing two aspects: on the one hand, system level functional verification of the IP is completed by VCS and Ncverilog tools. Simulation results show that the IP logic design is completely correct. On the other hand, To achieve the prototype test and accelerated hardware verification of the IP by the use of Altera FPGA. Validation results showed that the IP meets the requirements of the technical indicators of the design. The IP back-end design flow is validated by the 0.18μm CMOS process.