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Study And Improvement Of The ESD Test Method And I/O Protection Technique For MCU

Posted on:2016-04-23Degree:MasterType:Thesis
Country:ChinaCandidate:Y XiaoFull Text:PDF
GTID:2308330470964526Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
With the increasing number of electronic products and electronic system, the electromagnetic environment of electronic equipment have become more and more serious. So it is urgent to solve the problem of how to make electronic device be compatible with other devices with little interference in common electronic environment during normal work. At the same time, this problem has received more and more attention. This is also the purpose of the research on electromagnetic compatibility. Now, with the advance of very large scale integrated circuit technology,feature size has become smaller and smaller, thus electrostatic discharge become more and more harmful to IC reliability. According to statistics, chip failure cause by ESD/EOS account for about 30%-50% of the total failure number.Now, there are mainly two ways to solve the ESD problem and realize the protection for the chip. One way is off-chip protective unit, the other on-chip protective unit. For on-chip protective unit,This article is based on the existing system level ESD test method. According to the problem in the testing process, an improved microprocessor ESD test method is proposed. And I/O protection circuit is also optimized. At early design, we don’t konw the circuits’ actual ability of processing ESD current. So we need to adopt corresponding chip-level ESD testing method to gauge the on-chip protective unit’ability of processing ESD interference. Trough amounts of repeated tests and re-design on the chip, when the chip meet the test requirements the chip will be assembled into the market.The first part introduces the microprocessor ESD test method. Fist of all,according to the system level ESD test method of IEC61000-4-2 standard, the deficiencies of the system test method is summarized. The test method is improved reference to freescale’ existing powered-on chip level ESD test. In this paper, the test environment, the test hardware circuit design, PCB design, test software and test process is described in detail.The second part mainly introduces the improved ESD test method. During freescale’ powered ESD test, welding the chip to the PCB is not only a repetitive process but also time consuming. The feasibility of the method is validated by a large number of repeated experiments and the processed experiment data.The third part study the ESD protection circuit for microprocessor. According to the characteristics of the ESD pulse and test results, I/O circuits are optimized. And through the simulation analysis and the subsequent test, protection circuit is verified.
Keywords/Search Tags:Microprocessor, Electrostatic discharge, IEC61000-4-2, ESD/EOS, PCB
PDF Full Text Request
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