The Research And Design Of Dual-mode Decoder Based On LDPC/Turbo Code

Low-density parity-check(LDPC) codes and convolutional Turbo codes are a class of error correction codes which perform is close to the Shannon limit, besides that they are widely used in modern communication systems and be required in a multi-mode baseband receiver. In addition the dual mode even multi-mode decoder is required urgently in the future communication systems. The current domestic research on multi-mode decoder restrictions in one code with different code rate and length. In the existing concerned foreign literatures, the research focused on the design of compute unit, whereas no particular design for how to share storage unit. In this paper, aiming at the shortcomings of the existing research situation we put forward the corresponding improvement innovative scheme based on the LDPC/Turbo dual mode decoder which apply to 802.16 e standard and 3G/4G standards.Firstly, by study of different decoding algorithm of LDPC code and Turbo code, we selected TDMP and Log-MAP algorithm as the decoding algorithm of LDPC and Turbo codes. From the study of simplified algorithm of Turbo code, and according to the decoding performance we choose look-up table method to simplify the Log- MAP algorithm, and the same simplified method was applied to the LDPC code, the simulation results show that the TDMP algorithm based on look-up table method also has a good decoding performance. In this paper, we design a kind of dual-mode decoding calculation unit(CPU) based on the above decoding algorithm, this unit invoke two table lookup table, compared with the existing literature we need look-up table form to a third less.Secondly, according to the similarity of decoding process, we innovative proposed a shared storage scheme. Because the number of variables needed to store about LDPC is larger than the Turbo code at the same time, and the total variables of LDPC need less storage than Turbo code, so if the storage unit adopts the design of maximizing will cause the waste of resources. Therefore, we put forward a way of storage unit splicing and sectional to minimize the consumption of storage unit.The results show that the proposed dual mode decoder need less resourse consumption than the sum of signal mode decoder of LDPC and Turbo codes, the consumption of logic element is 33% less than the exiting research. In LDPC decode mode, the maximum occupation ratio of memory is 52%, and 98% in Turbo mode. Comparing with the theoretical occupancy the gap is respective 5% and 2% in this paper with 13% and 10% in the literature [45], we can draw the conclution that our design is more reasonable. What’s more, the storage consumption of every bit is 34 bit, and 39 bit in literature [45]. Under the same code length and rate, the consumption in this paper will be saved 13%.It can support the decoding of six rates for LDPC in 802.16 e standard and Turbo codes in 4G for rate 1/2 and 1/3. The total consumption of logic element is 6.08 k, and 143 k bits for memory units, the maximum frequency is 62 MHz. Compared to other literatures, the proposed dual mode decoder can reduce the hardware resource consumption effectively, and can achieve the decoding of LDPC and Turbo codes.