Design And Implementation Of High Speed Analog Acquisition System

The high-speed data acquisition system is widely used in both civil and military application. And the system through CPCI bus has solved the bottlenecks in data transmitting. A novel high-speed analog acquisition system is designed and implemented in this thesis, which has the function of data acquisition and data storage and data broadcast. The demodulated data and channel detection information broadcast via Ethernet interface.Based on the understanding of the domestic and foreign present situation to the high speed analog acquisition system and the problems need to be resolved later, put forward a solution of a kind of CPCI bus technology in high speed analog acquisition. Paper uses a 14 bit AD conversion chip as the core chip in analog to digital convers ion. Also need to consider some compliance with design in parameter and error requirements when selecting the chips. NAND FLASH chip is used as a storage medium in the entire system. This introduction of solid state storage technology also makes the whole system to be in the data storage capacity is relatively stable, and can meet the demand of design. However to the control chip of the system uses the FPGA chip of Virtex-6 family. The FPGA chip is the role of control analog acquisition board and acquisition and playback work, but also the configuration of a stable clock for data collection.After considering all of these requirements, in the design of front end circuit, clock circuit and power circuit, according to the requirements of the design and selection of chip give the principle diagram design of concrete. At the same time for solid state storage control technology is combined with the design index points to the need to pay attention to in the design of hardware circuit processes. Then as the key connection of the whole system, puts forward the design process of software, including the control software and storage control software.High speed analog acquisition system for final can use 12 bit, AD chip 1GSPS sampling rate of data acquisition, and use 16 bit, DA chip 1GSPS sampling rate data playback.