Real-time Image Despun With Stepless Zoom Technology Research And The Realization Of Fpga + Ddr

In recent years, with the development of digital image processing technology, theracemization of the real-time image and stepless zoom technology have been widelyapplied to all walks of life. Whether it is the infrared pod system, optical sights andother military equipment or production monitoring and intrusion alarm civilian fieldboth inseparable from the image racemization and stepless zoom technology. But usingtraditional image racemic and scaling algorithm, the image will become smooth, theedge of the characteristics of the image will be damaged, which will affect thefollow-up image processing algorithm, so the image of racemic and stepless zoomingalgorithm is still a very important topic.The image of racemization and scaling algorithm are analyzed in detail in thisthesis, some of their commonalities are also summed up. According to the actual needsof the project, the coordinate transformation formulas and interpolation algorithm arefusion. In analysis and comparison of the common interpolation algorithm, the gradientof the interpolation method based on edge is introduced, the gradient interpolationmodel is also established, and interpolation method is improved based on thecombination of gradient interpolation and bilinear interpolation. Eventually Modelsimsimulation with the improved algorithm is used and the results shows that the imagecontrast is significantly improved and edge noise the simple gradient interpolationbrought is also reduced, which retains the edge information well. To some extent thisresults show that the improved algorithm is feasible, which can meet the project designrequirements.At present, the development of image processing technology is moving in thedirection of the high-resolution, image data related to image processing algorithms needto be addressed more and more, the traditional hardware platform usually usedmemory-chip RAM, off-chip SRAM, off-chip SDRAM, etc.. Whether considered fromthe cost or storage capacity, they are difficult to meet the needs of the project;Especially some military design, blindly use the on-chip RAM as buffer, not onlywastes valuable FPGA’s chip resources, but also with the requirement of the development of high-resolution the middle and low FPGA has been graduallyabandoned and accordingly the R&D costs will increase. Therefore, in this thesis, weput forward a new kind of hardware platform with low-cost and high-resolution, withmiddle and low FPGA as the core processing chip, which is with high-speed, largecapacity, and low-cost DDR SDRAM as buffer, and debugging successfully, which canmeet the actual requirements of the project well.Architecture based on FPGA+DDR brings the advantages of cost and storagecapacity, but we must overcome the difficulties for the operation of the DDR readingand writing. By adjusting and improving the implementation of the algorithm, withon-chip asynchronous RAM as a link, with the assembly line thought, we successfullyrealized the operation of the DDR reading and writing, the improved algorithm wastransplanted to the new hardware platform successfully.