Research Of High Speed And High Resolution ADC Test

ADC is the key interface chip between analog world and digital world, which is popularly used in many areas such as video, wireless communication and military application. As the rapid development of electronic communication, ADC is becoming higher speed and higher resolution. Because of technology and cost, sometime ATE can’t meet the test requirement from high end chip. For the production test of high speed and high resolution ADC, it’s difficult for ATE to test them due to output sampling clock and linearity of signal source. Therefore, this paper will do some research and exploration on how to test high speed and high resolution ADC.This paper selects the chip AD7626 from ADI, which is 16 bits and maximum 10 MSPS, to test its static and dynamic parameters on UltraFlex of Teradyne. For the datasheet, SNR of AD7626 is 91dB with 1 MHz input signal, which requires that clock jitter must be less than 4.5ps. However, the jitter of digital channel on high end ATE is normally less than 4ps, and it’s is 8ps in case of UltraPin800 of UltraFlex. It’s hard to meet the test requirement. To fix this problem, the solution proposed by this paper is to use SMA100A and AD9512 to provide low jitter external clock with the value of 0.5ps. The INL spec of AD7626 is±1.5LSB, and the spec of TurboAC on UltraFlex is 2.6 LSB (ENOB=16.7). It can’t meet test requirement if we test DNL/TNL by ramp histogram. Since TurboAC uses the techniques such as oversampling, noise sharping, etc. It provides better control over accuracy of sine wave than ramp. That’s why this paper uses sine histogram to measure DNL/INL instead of ramp histogram. The test results are that SNR=90.7dB, THD=-85dB, DNL=0.28LSB, INL=0.8LSB. It’s shown that the solution of this paper can meet the test requirement of AD7626...