Design And Implementation Of Configurable Dual-Channel Pulse Compression

Pulse compression technique is widely used in the modern radar system, which can improve the detective distance and resolution. Nowadays, the radar has developed from analogical type to digital type, which can advance the performance of the radar in processing speed, reliability and so on. The implementation methods for pulse compression are FPGA, DSP and ASIC. However, the devices of FPGA and DSP not only cost highly, but also are difficult to meet the real-time requirement in the radar signal processing. With the development of IC, the processing ability of single chip has been improved. As a result, pulse compression technique with the ASIC implementation can meet the real-time requirement in the radar signal processing and the mass production can reduce the cost. ASIC implementation for radar signal processing is worthy to discuss.Based on the theories of radar signal processing, the ASIC implementation method for pulse compression technique is mainly discussed in this paper. Firstly, the radar signals and the algorithms of PC are researched. Secondly, according to the design requirements, a 32 to 4096 variable point and pipelined SDF architecture FFT processor based on radix-2 algorithm is proposed, while the correlation circuit has been optimized. Based on the above proposed FFT processor structure, a dual-input mode FFT structure and a configurable dual-channel PC structure are proposed. The design has many advantages in low cost, area efficient, flexibility and reusability. Finally, the front-end ASIC design, function verification and timing analysis of these two parts are completed.In this paper, a verification platform is built with Matlab. The function verification of FFT processor and PC circuit are performed. The relative error of FFT between hardware processing and algorithm simulation was about 10-5. At last, the PC circuit is synthesized with the Design Compiler® in the SMIC.13 standard cell library, the formal verification with the Formality® and static timing analysis with the Prime Time® for the gate-level netlist are performed.