Design And Realization Of Low-power HF DSP+FPGA Platform And Data Transmission Protocol

HF communication has be an important technical means of modern information systems. Due to its characteristics, HF communication plays a unique role in international communications, flood relief, beach rescue and military communications, etc. Currently, the third generation HF communication system is at a stage of rapid development. Broadband, high speed and low power are the development directions of the third generation HF communication system.According to the above system design goals, the hardware design with TMS320C6748 DSP+FPGA as the core signal processing module is given in this thesis. Each module of the HF hardware platform is designed and their function is tested. These include power management module, clock module, the hardware resource allocation, DSP chip serial FLASH bootstrap module and DDR2 memory module. Because UPP interface is one of advantages of the TMS320C6748 DSP, data exchange between the DSP and the FPGA via the UPP interface is designed and implemented in this thesis. The business type, test process and tested results about performance of HF broadband modem has been described.Secondly, according to the technical standards of the third generation HF communication systems, the data link layer protocols about traffic management protocol and data transmission protocol are studied, including high speed data transmission protocol and low speed data transmission protocol. On this basis, the new data transmission protocols about terminal interface protocol and protocol data units are given. Error control and adaptive variable speed are discussed in this thesis.Finally, the designed data transfer protocol on the existing HF modem hardware platform is programed, and the protocol functions are verified.