The Research And Design Of 10Bits SAR ADC Applied In Digital Products

In these years, digital products are widely used in the field of mankind daily life such as digital camera, scanner, vidicon, mobile phone, laptop, wireless router, STB and so on. Humans have increasing expectation on every new generation of digital products. Analog to Digital Converter (ADC) is a key module used in digital products which plays an important role in bridging the gap between analog signal and digital signal.The features of Successive Approximation Register ADC (SAR ADC) are low power dissipation and small chip area. It consists of four key modules including Sampling and Hold(S/H) module, Digital to Analog Converter (DAC), Comparator and SAR logic module. In recent years, with the feature sizes of CMOS devices scaled down, the sampling speed of SAR ADCs has been greatly improved. It will have huge commercial value to design a SAR ADC applied in digital products.A 1 Obits 10MSPS SAR ADC applied in the digital products is designed in this paper. The chip works under 1.8V power supply. A set-and-down capacitor array switching method is used in this SAR ADC to decrease the chip area, reduce the power dissipation and improve the conversion speed.Sampling and Hold(S/H) modules are the interface circuits of SAR ADCs, which are directly connected with the analog input signal. A voltage bootstrap switch is used in this paper as sampling switch to improve the linearity of S/H module. Top plate sampling technique is used in this S/H module to increase the sampling speed.The founction of DAC applied in SAR ADCs is to supply reference voltages for quantization. In this work, we employ a kind of charge redistribution DAC to achieve low power dissipation and reuse the DAC as the sampling capacitor to obtain small chip area. We utilize a partial common-centroid layout strategy for the capacitor array of DAC to reduce the influence of capacitor mismatch and parasitic capacitance of interconnection.The founction of comparator applied in SAR ADCs is to quantize the analog input signal. We utilize an improved structure of comparator to gain low power dissipation, low input offset voltage and high comparing speed. Through carefully designing the sizes of devices, we successfully reduce the kick-back noise which will influence the input signal of comparator.The SAR ADC is designed based on the Global Foundries 0.18μm CMOS process. We have tested it by using Cadence. The simulation result shows that the SNDR of proposed circuit is 59.04dB, the ENOB can reach 9.51 bits, and the FoM can reach 142fJ/conv-step. This design reaches the design goals and satisfies the basic requirement of digital products.