FPGA Hardware Design For HSUPA MAC-es Protocol

HSUPA(High Speed Uplink Packet Access) is an evolutionary technology inWCDMA system introduced to improve uplink data transmission rate and the systemcapacity. By using E-DCH composite transmission code, optional shorter time intervals(TTI), and HARQ retransmission mechanism the uplink data plane protocol can achievehigher throughput.Firstly, technical characteristics and development status of WCDMA HSUPA areintroduced. The special structure and characteristics of HSUPA, and the key technologiesof HSUPA such as Node B controlled scheduling, HARQ, and shorter TTI are described.Secondly, in order to achieve greater uplink data transmission throughput, this thesisanalyzes the MAC-es protocol layer in FPGA implementation process. Based on Veriloglanguage, it designs and implements this system, including the MAC-es protocol andimplementation scheme of FPGA system based on the sub layer layer system architecture,which focuses on the analysis and flow processing method and the solution to MAC-eslayer packet PDU HSUPA packet reordering problem.Finally, we write test cases, built the simulation testing platform, and use ModelSimsoftware for tests on module functions and this system. The simulation results show that,the proposed scheme can achieve the design goal, and is feasible in practical systems.