Based Design, The Fpga Sdh Multiplexing And Demultiplexing

In 1984, the Synchronous Optical Network was proposed to eliminate mutually exclusive of the light interface, and it was marked as a kind of brand-new transmission network technology system. In 1988, the International Telecommunications Union Standards of International Telex-telephone Consultation Committee approved the concept, and SCONT was renamed as Synchronous Digital Hierarchy (SDH), at the same time. By constant development and improvement, SDH was recognized as the unified standard of the transmission network. It was applied mainly in optical fiber communication, microwave communication and satellite communications, and became the generic technology system. The elements of SDH are rather complex,so does the agreements and structure. Because of causations above,ASIC is the trend of evolution,core circuits of SDH elements are implemented by ASIC.The paper provides the solutions of SDH synchronous multiplexing, and the realization of multiplexing in FPGA. The design includes the STM-1 signal multiplex modules and the scanning tunneling microscopy STM-64 by STM-64 interpolation points out STM-1 module. The design could be made as a new device module, and reduce the cost of SDH equipment.This paper first introduces the principle, analyses the SDH technology index, and affords the way of multiplexing and demultiplexing. After that, it verifies the viability of design in the FPGA developing board. The detection signal is verified through a special DS3 chip and DS3 multiplexed STM-1, via the modules eventually gets DS3 signal. Besides the short design cycle, low cost, according to actual needs, the test design could be put the parts of the special chip.The design divides into the several modules. If not require the high rate signals, they can only choose the low rate signals, and the high rate of signal is retained. With the system upgrading, the high speed signals can directly be used, in order to meet the needs.