Research On Multilayer Stack Bonding Technology For System In Package

Three dimensional packaging based on TSV technology is the fourth generation ofpackaging industry, with better performances of higher level integration, higher speedinterconnection, shorter interconnection distance and less interference, it is the mainstreamin the direction of the future packaging development. As one of the key technologies ofthree dimensional packaging, bonding process can realize mechanical interconnection andelectric interconnection between the chips, which has a huge impact on the performance ofthe product. But most of the current bonding methods need high temperature and long time,and reduce the efficiency, which damages the product reliability, therefore, achieving lowtemperature bonding is very crucial for three dimensional packaging. While Cu-Sn eutecticbonding has good conductive and thermal performance and the advantage of low bondingtemperature and high using temperature, so it is very suitable for three dimensionalpackaging and became the hot spot of the current research on three dimensional packagingbonding technology. Cu-Sn eutectic bonding mainly through melting metal Sn to reduce thereaction conditions and accelerate the reaction rate, so as to realize low temperature bonding,the melt point of Sn is232℃. Multilayer stack technology based on TSV process is theemphasis and difficulte point to improve the performance of packaging products, which iscomplicated process Combined with etching, electroplating, bonding and alignment. Thispaper will focued research it and develop a stability stack technology with high efficiencyand high yield for three dimensional packaging. The main contents are listed as follows:Firstly, the principle foundation of Cu-Sn low temperature bonding was analyzed, thelow melting point metal Sn will melt in the bonding process, the existence of melted liquidSn can accelerate the mutual diffusion of Cu and Sn and achive low bonding temperaturewith low pressure and high reaction rate; Secondly，developed a reliable and high yield preparation technology for chip samplewith TSV and Cu/Sn micro pads, mainly including lithography, film technology, silicondeep etching, TSV electroplating copper, silicon wafer thinning, electroplating Cu/Sn padsetc., and preparated5batches of1000pieces sample chips; and also esearched the influenceof pressure, annealing temperature and annealing time on Cu-Sn bonding process andoptimized the bonding process through many experiments, and finally got the optimumprocess condition, the bonding pressure was0.5MPa, the annealing temperature was260℃and the annealing time was10min;Thirdly, realized the mutilayer stack boding through Cu-Sn low-temperature bondingtechnology, the stacked layers increase gradually by changing the Sn layer thickness, andeventually achived the10layers stacked moudle, the alignment was precision and thebonding was tightly; and then tested the mechanical strength and electrical properties of thestack bond structure, and also high temperature test, thermal shock test and high temperaturehigh humidity test were carried out, all the test results showed that the stack tchnology couldmeet the requirement of3D packaging;Lastly, put forward a new type of chip alignment method and device, completedpreliminary design and manufacture of the device, and then improved it, and the device wasused for multiple chip alingment test, the alignment accuracy was4-6μm.