Study Of Small High-speed Signal Acquisition And Storage Test System

The data acquisition system is an important component of the instruments withmeasurement technology.With the rapid development of information technology,the demandof the sampling precision and data processing speed is becoming more and more high. Thisarticle proposes a method to realize a small high-speed acquisition and storage system testedon high frequency signal of the online dynamic coding.According to the characteristics of the dynamic coding signal, the processing link and thesampling requirements of the signal are analyzed.Combined with the actual situation of thetest environment, choosing the high-speed AD converter, a high performance FPGA andappropriate SRAM devices.The anti interference and electromagnetic compatibilitytechnology, signal integrity analysis technology, ping-pong storage technology are used tobuild high speed collection storage test system. In the process of the study, the system isanalyzed according to the chip selection,the signal transmission method, the storage methodof signal and the later multi-layer PCB design.The corresponding preventive measures ofinterfering signal integrity and accuracy during the signal transmission are proposed. Makethe simulation of the key network parts in the PCB.The optimal layout and wiring constrainedof the device are formulated. The experiments validate that the acquisition and storage testsystem can accurate measurement and has not lose a data.The hardware testing system is composed of signal attenuation module, signal differencemodule, A/D conversion module, power module, FPGA control module, SRAM memorymodule, clock module, USB reading and write module, level conversion module etc.In the design of sequential logic system, the resources of FPGA are utilized reasonably,such as PLL, LPM_buris, counter, LVDS interface and so on.The PLL provides precisedifferential clock signal for the ADC. LVDS interface accurately receives the digital signalfrom theADC and reasonably allocate the signal to the SRAM. Finally, as the results of the analysis to the test, the cause why the results are non-idealare found by the segment debugging,and the improvement methods of the test system are putforward.