Design And Research Of Digital Controlling Circuit In Fieldbus MAU Chip

As industry controlling local area network, fieldbus technology has been widely appliedin industry field. Meanwhile MAU(Medium Attachment Unit) chip is the essential part forbus-powered instruments obtaining energy and exchanging data. At present the research ofMAU has a significant meaning because of the importance and the high technology difficulty.MAU chip is the large-scale mixed signal integrated circuits with high system complexity.This paper presents the design and implementation method of digital circuit blocks in MAUchip. This subject comes from an actual engineering project and the goal is to design acompatible MAU chip with a foreign chip model. There exists large difference betweenoriginal and present process, therefore the design decides to adopt the method which reversedesign combined with forward design. In order to master original chip functions, deep analysishas been done firstly. Using Chip Analyzer software to extract and clear up circuits accordingto the function principle, then analyzing each function module specifically including thesource regulator module, the sending function, the receiving function module, the digitalcontrolling module, trimming burning circuit, DC/DC converter and others modules byreferring to data. Among these, the main function of digital circuit is to decide system workingstate according to the state signal from all the function blocks, and is responsible formonitoring the rationality of communication data. In addition to these, trimming burningcircuit, DC/DC converter and other modules based on digital circuit have been contained inthis paper. In the foundation of fully understand original circuit, the circuits are redesignedwith HHNEC0.35um BCD process. Keep original design but modify the transistor parametersin the condition of little difference process. To change by a large margin including circuitstructure even performance when there exits the big difference in process. The new designmeets the property requirement through simulation verification. Finally, the layout design haspassed DRC and LVS checking. The chip has been checked and accepted, it is waiting fortape-out testing now.