Design And Optimization Of SATAIP

Parallel bus PATA proposed so far have almost30years of history, its flaws have been a serious impediment to the further development of storage performance, has been replaced by the SATA bus. SATA hard disk interface protocol as a new generation has been developed to the third generation, the transmission rate has been developed from the first generation of150MB/s to600MB/s, and the use of point-to-point data transfer, built-in error correction check unit supports hot plug, be able to support RAID mode. SATA storage has been widely used to present, only two companies will provide premium high-performance SATA IP, there is no domestic the SATA IP development, so the design for FPGA applications SATA IP is of great significance.The SATA protocol overall detailed analysis of the SATA soft-core build hierarchy. The soft core of the side of the device hierarchy is divided into the application layer, transport layer, link layer and physical layer of the four levels; highlighted based on the physical level of the protocol design Groundhog SATA protocol link layer, transport layer, and a command layer. NCQ SATA protocol function, and FPGA-based SATA IP optimized design and testing, through the comparison of the data showed that the superiority of the optimized way. The paper focuses on the rate of the SATA protocol is the mainstream SATA protocol,Sequence queuing algorithm to the SATA IP read rate is increased50%to140%, while reducing the power consumption and the loss of the hard disk.