The Design Of TCAM Testability

Ternary content addressable memory (TCAM) is essentially a hardware-based search engine; and it was presented on the basis of Binary content addressable memory. It has more flexible than ordinary BCAM in storage and search capabilities. The existence of such a special function of TCAM makes it more complex than the structure of BCAM. The existed test algorithms for BCAM error detection has been unable to meet the demand of TCAM, the existed error detection method for high-speed large-capacity TCAM have a lot of shortcomings on the test complexity and detection coverage. However, with the demand of high-performance network router for large-capacity and high-speed TCAM continuous improve error detection for high-speed and large-capacity TCAM has become a key research direction, so the proposed high-speed and large-capacity TCAM testability design has important theoretical and practical value.In this paper, a preliminary study of error detection problem of TCAM is carried out, and two error detection algorithms and a detection circuitry are proposed. First of all, a new improved algorithm based on existing March-Like is proposed. The proposed algorithm requires2N write operations and2B+4compare operations to cover100%of targeted comparison faults and delay faults for an N*B-bit TCAM via Hit and Priority Address Encoder outputs. The proposed algorithm reduced over60%compared to the previous March-Like algorithms. Moreover, in terms of improve error detection coverage; the paper put forward a new QZDTest error detection algorithm for high-speed large-capacity TCAM. The new kind of method in the aspect of error detection can not only cover100%inner-cell TCAM cell faults and delay faults but also can cover100%intercell TCAM faults. In the term of test speed:the proposed algorithm use their own test vector generator te^t vectors to complete N*B-bit TCAM error detection through5N write operation and6B+12search operation, the test speed is the same as practical application. Further, in the design of the detection circuit, it use finite state machine to control the shift register to complete the TCAM storage and comparison operations, substantially reduces the cost of the test circuit. In the design of judge circuit, by inserting an inverter and a selection circuit after amplifier, it can get error signal through Hit determination signal and output the highest priority error address directly through the address priority encoder. Circuit simulation results show that the algorithm can fully coverage TCAM detection in a single cycle.The proposed design for testability is very suitable for error detection in large-capacity and high-speed TCAM storage unit. Such as high-performance network router, packet forwarding, address classification, network firewalls, virtual private network filtering and other advanced network applications in TCAM error detection.