Design Of A Low-Power And Soft-Error Tolerant TCAM System

For solving high power-consumption and serious soft-error of Ternary CAMs (TCAMs) in deep sub-micron era, this paper presents a new TCAM soft-error hardening system based on scrubbing mechanism of embedded DRAMs (eDRAMs).This paper designs a novel NAND-type matching line for reducing the searching power of this soft-error hardened architecture. Double hamming encoder and correcting decoder circuit’s working-zone can correct all one-bit upset and some two-bit upset.3T-DRAM cells not only increase the soft-error immunity of the TCAM system, but also optimize the scrubbing timing. As results, this architecture has taken advantage of the higher critical charge and periodical scrubbing mechanism of DRAM to rewrite the right data which corrected by hamming correcting circuit to TCAM array continuously.Firstly, this paper introduces the architecture briefly and analyses the low-power and radiation-hardened of TCAM all over the world. Secondly, this paper has improved greatly by TCAM matching line, hamming correcting circuits and eDRAM array to improve the three shortcomings of the former design in deep sub-micron era. Thirdly, we design three solutions for these shortcomings and simulate them to guarantee the correct of the solution. Finally, we make a whole 16x16 bits low-power and soft-error tolerant system for performance simulation without soft-error and correction simulation with some upset.The simulation results show that this low-power and soft-error hardened TCAM system proposed in this paper is Strong immune to all one-bit soft error and some two-bit upset which happened in each independent working-zone. Compared with unhardened TCAM circuit, the search power-consumption of this system has only increased 29.8%. What’s more, the speed of writing operation and searching operation will not be affected by hardening circuits. As results, this architecture has certain value on today’s TCAM research about low-power and soft-error immunity.