| With the continuous improvement of analog CMOS processes and the development of digitalsignal processing technologies, the Sigma-Delta ADC has become a hot research topic in the fieldof microelectronics. Among the many types of analog to digital converters, the Sigma-Delta ADCcan achieve higher accuracy than other ADCs for its advantages of over-sampling, noise shapingand digital filtering techniques, and are widely used in the field of wireless communications.A high-speed medium-accuracy Sigma-Delta ADC, applied in UHF RFID reader base-bandreceiver is designed and implemented. This design is divided into two parts, analog modulator anddigital down-sampling filters respectively. Firstly, the basic principles and the structural ofSigma-Delta ADC is introduced, and then the system-level modeling and simulation of themodulator is implemented based on MATLAB/Simulink, and the impacts of non-idealities on theperformance of Sigma-Delta modulator is analyzed simultaneously. Next, the transistor-level circuitand layout of the modulator is designed on this basis, including operational amplifier, comparator,and clock generation circuit. Secondly, the advantage and effect of digital down-sampling filters tothe Sigma-Delta modulator is elaborated, and three cascaded filters are designed according to theparameters of the modulator, including CIC filter, CIC compensation filter and half-band filter.After finishing the system-level design and verilog code simulation, the performance of the filtersis verified on the FPGA PCB board. Based on the result of simulation and verification, the digitaldesign flow of the filters is completed, including logic synthesis, placed and routed, static timinganalysis, physical verification and etc. Finally, the layout design and post-simulation of filters isimplemented.A2ndorder one bit modulator and back-end digital down-sampling filters is designed based onSMIC0.18μm CMOS process with1.8V supply voltage. The modulator, which adopts fullydifferential switch capacitor circuits, with sampling frequency of64MHz, over-sampling rates of32can process1MHz bandwidth range. The passband ripple of digital down-sampling filter is less than0.01dB and stop-band attenuation more than70dB. The result of simulation show that53.8dB ofoutput dynamic range is obtained when the input signal is500kHz. The layout size is1.2mm x0.7mm, with power consumption about60mW, and can meet the design requirement. |
