The Research And Implementation Of 5Gbps High Speed Serial Interface Circuit

As a result of the effect of the non-ideal such as jitter, skew, synchronization and crosstalk, the parallel transmission system is confronted with the huge challenge that its transmission rate can not be increased further. Serial transmission gradually becomes the primary option in high-speed transmission system in deep sub-micron technology, In serial transmission system, the data is often transmitted with low-swing. In this way, the serial transmission system can reach high data rate with low power consumption and low cost. LVDS (Low-Voltage Differential signal) and CML (Current Mode Logic) are the serial high-speed interfaces based on low-voltage and low-swing differential transmission technique. Both of them are widely used in PCI-Express and high-speed SerDes. However the data rate of the traditional LVDS can just reach 3Gbps nowadays. A pseudo LVDS (PLVDS) circuit and a CML circuit are designed in this paper to meet the requirement of the independent PCI-Express application whose data rate is 5Gbps and above.On basis of high-speed data transmission theory, this paper begins with the analysis of the non-ideal that has an effect on the signal integrity and the analysis of the behavioral characteristic of the transmission line. Afterwards, the design considerations of high-speed serial transmission system on circuit and layout level are proposed. Finally, the transceiver of the PLVDS and CML circuits are designed and many improved schemes are brought forward. The free-skew single-to-differential circuit can well mitigate the problem of skew, the level-shift circuit can quickly transform the low-voltage signal in kernel to the high-voltage outside with accelerated transistor, the current switch circuit make the output more stable with double common mode feedback technology, and the differential pre-emphasis circuit emphasis the drive ability and can reduce the inter-symbol interference. At the same time, many critical technologies are adopted in the CML transceiver circuit. The active negative feedback and active inductance can not only widen the bandwidth of signal but also enhance the performance of the circuit, reduce the complexity, low the power consumption and minimize the chip area. Equalization technology minimizes the signal distortion caused by the effect of the transmission line and the inter-symbol interference. Meanwhile, a three-stage Cherry-Hooper limiting amplifier is designed in order to amplify the output voltage of the equalization circuit which the comparator can identify.Two high-speed serial PLVDS and CML interfaces are realized in 0.13um CMOS technology. The simulation result show that the data rate of the two interfaces both can reach 5Gbps. Both of them can well meet the requirement of the PCI-Express application.