SoC Design And Implementation Of Dynamic Image Edge Detection Based On LEON3Open Source Processor

Dynamic image’s edge detection is an essential content of many complex dynamic imgae tracking and recognition system. However, in the existing tracking and recognition systems, image processing speed has been a design bottleneck. In order to improve system processing speed and performance, this paper achieves a part of algorithms in the form of hardware, which will accelerate the algorithm processing speed.At present, in the case of large amount of data processing or real-time demanding applications, the existing microcontroller or DSP-based hardware implementation of edge detection algorithms can’t give full play to the advantage of hardware acceleration, because its nature is still relying on the serial execution to complete data processing and the processing speed is limited by pipeline.In this paper, a SoC design of dynamic image edge detection based on LEON3open source soft-core processor is proposed, which is an ASIC design for dynamic image edge detection with a CPU. This system implementataion fully shows the high-speed and flexibility advantages of hardware design.This paper presents two algorithms for image edge detection and also given two SoC programs:the image edge detection algorithm IP core based on APB bus and the image edge detection algorithm IP-core based on AHB bus. First of all, verify algorithms’ performence using MATLAB; then, use hardware description language to achieve the algorithms and use Modelsim to do timing simulation. For the APB-based design, image acquisition, edge detection and image display are packaged in one IP-core with APB bus interface. For the AHB-based design, a camera IP-core is designed, which transport datas from camera to SDRAM directly with DMA. At last, these IP-cores will be mounted to the LEON3classic SoC architecture for the simulation and physical test.This system achieved22～25frames per second, the best resolution of400×240and640×480dynamic edge detection, and the average data delay is70～80system clock. This system is flexibility and reliability, small footprint, fast, has a broad application prospects.