The Study Of High Reliability Architecture Design Based On LEON3

This thesis focuses on the study of space high reliability processor design and verification.Space high reliability processor is designed for space platforms, such as on-board computer system. Space radiant environment is the special factor we should pay attention to when we design space high reliability processor.Firstly, it analyses the space radiant environment, gives out several radiant efforts which have impact on the processor, discovers that the logical impact of these space radiations on processor are in data stream and control stream.And it gives out the mainly space processor design methodology aimed at the space efforts.Lately, this thesis pays more attention on the study of the Single Event Upset (SEU) based on LEON3 and high reliability architecture design based on COTS technology.1. Reliability evaluation platform based on RTL fault injection (RTLFIA).We have designed and implemented the processor reliability evaluation platform based on RTL fault injection-RTLFIA,with its features are efficiently and accurately,and have analyzed the LEON3 using this platform,and have gotten some data about reliability of LEON3.2. High reliability IU prototype (HRIU).we have studied the mainly high reliability architecture design technology, included Hamming Code and Triple Modular Redundancy (TMR), have given out BLOCK-TMR.Then, we have implemented the high reliability IU prototype (HRIU), and have ran many benchmarks to test its availably and its overhead.HRIU can avoid the impact of single SEU on processor, and can check out the impact of multi-SEU on processor.3. A new control flow check algorithm (KDCFCA).Aimed at dealing the fault of control flow check in some space computer we designed, we have given an on-chip control flow check mechanism and studied the mainly control flow check algorithms, have done some improvement and have gotten the new algorithm: KDCFCA, we have found it can work well in control flow check.