The Design Of Parallel HEVC Decoder Aiming At Ultra High Definition Applications

To meet the ever increasing demand for ultra high definition video inconsuming electronics area, ITU and ISO have collaborativelystandardized HEVC. Challenged by the demanding computationalcomplexity of UHD applications, the realtime decoding performance ofHEVC has a critical impact on the comerialization of this standard.To solve the problem above, we study the design of realtime parallelHEVC decoder for UHD applications on a symmetric multiprocessingplatform. In the framework aspect, we discuss the parallel data-level andtask-level decompensation methods that are beneficial for the scalabilityand load balance of decoder. Then we implemented the system with highefficient synchronization and storage mechanism in object orientedperspective. With respect to platform optimization, on one hand, we takeadvantage of the SIMD instruction set of Intel CPU to accelerate thecomputation of inverse quantization, inverse transform and interpolationfiltering. On the other hand, we adjust the processor affinity to combineCPUs and threads in a way that leads to less context exchanging cost.According to the test condition and test materials used during thestandardization of HEVC, we assessed the performance of our decoder anddemonstrated its realtime processing ability in UHD and HD applications.This dissertation is benefical for research regarding decoder performanceoptimization in corresponding industrial and academic areas.