Research On Design And Power Management Of HEVC Decoding On Heterogeneous Architecture

With the increase in network bandwidth,video-based application data traffic dominates the Internet.At the same time people put forward higher requirements on the video clarity,fluency.The next-generation video coding standard High Efficiency Video Coding(HEVC/H.265)is capable to provide high resolution videos at double compression compared to the widespread Advanced Video Coding(AVC/H.264)standard.Several novel coding techniques have been adopted to improve the compression and parallelism of HEVC,including variable block size,independently processed video tiles and multi-level filtering.However,the new technology not only improve the coding efficiency of HEVC standard,but also increase the coding complexity,meanwhile,the decoding difficulty has a corresponding degree of increase.According to statistics,under the premise of the same coding quality,its coder complexity increases by 5.2 times and the decoder complexity increase by 2.1 times compared to H.264/AVC.At present,some of the top electronics manufacturers,such as Intel,Apple,NVIDIA,AMD and Huawei and so on,have achieved the HEVC codec support through the ASIC hardware circuit.However,due to the high computational complexity of the HEVC decoder,real-time decoding of HEVC based on software is still an important research topic for embedded devices(mobile handsets,flat boards,etc.)with limited battery power and computing power.This article implements the parallelization of HEVC official test software HM and transplants it to low-power heterogeneous multi-processor system-on-chip with CPU and GPU.A large number of experimental data show that:GPU parallel architecture is very good to hide the decoder access delay,relatively narrows the processing time between video frames.What's more,the processing workload of each video frame and a coding parameter which can be easily obtained in the decoding process show a consistent change rule.According to the experimental process and the related experimental results described in the later chapters of this paper,we propose the workload prediction algorithm for the next frame of CPU and GPU decoding.Based on the predicted workload,the CPU and GPU cooperative DVFS strategy for specific application under the userspace controller running on the experimental platform is proposed.The DVFS strategy proposed in this paper effectively saves the energy consumption of decoding HEVC video.In addition,the accurate workload prediction algorithm allows a small frame buffer to ensure real-time decoding of the video,further reducing the overall overhead of the system.