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Research Of HEVC Coding Standard And Design Of HEVC Bitstream Parsing Module

Posted on:2015-01-15Degree:MasterType:Thesis
Country:ChinaCandidate:J J WangFull Text:PDF
GTID:2268330431453630Subject:Integrated circuit design
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As the resolution of the video content becomes higher and higher, it’s hard for the previous H.264/AVC coding standard to achieve the demanded coding efficiency, especially for video content with1080p or higher resolutions. HEVC, developed by JCT-VC, serves as the next-generation video coding standard. And the first final draft has been published in April,2013. HEVC video coding standard is able to achieve twice coding efficiency, compared with the H.264/AVC HEVC coding standard. The improvement in coding efficiency makes HEVC suitable for various video contents with higher resolutions. However, the tradeoff between increasing the coding efficiency and reducing the complexity when implementing the HEVC standard becomes an issue which needs more consideration.First, this paper gives a comprehensive analysis of HEVC coding standard by focusing on the improvement compared with H.264/AVC in many aspects, such as the partitioning of the picture, the parallel processing, the intra prediction technology, the inter prediction technology, the integer transform, the entropy encoding, and so on. Besides, it gives the architecture of the HEVC decoder and encoder after highlighting the key features of HEVC.Then this paper focuses mainly on the analysis and evaluation of the HEVC reference software (HM). The analysis of the reference software covers different settings for resolutions ranging from240p to1600p. The experimental results indicate that the HEVC standard can achieve twice coding efficiency at the cost of increasing the complexity slightly. In addition, this paper gives detail profiling results on the complexity of the HM decoder. In most situations, the decoding process is dominated by motion compensation, which takes nearly half the decoding time.Based on the evaluation of the HM decoder, this paper proposes the hardware architecture for the HEVC decoder. Then it gives the detail design and optimization of the bitstream parsing part. The simulation results indicate that the architecture of the HEVC decoder could meet the demand of HD video processing. And the output of the bitstream parsing part is the same as what’s generated by the HEVC reference decoder.
Keywords/Search Tags:HEVC, HM, HD video decoder, bitstream parsing
PDF Full Text Request
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