| HEVC,a new generation of video coding standard compared with H.264/AVC,is originally designed to save half the coding rate.However,due to the introduction of new features in HEVC,higher computational complexity has been incurred.With the development of the new chip integration process,the integrated core platform has become market-oriented and been successfully applied in related applications.In this thesis,the TILE-Gx36 integrated core platform was used carry out research.In this research,the work is aimed to find modules or syntax elements in HEVC which can be used for parallel processing,so as to utilize the processing cores on the platform appropriately and design the corresponding resource scheduling program which improved the video parallel coding efficiency.The content of this thesis can be divided into three schemes,as follows:(1)A highly parallel Inter/Intra joint WPP coding scheme is studied.Due to the low degree of parallelism of wavefront parallel algorithms in HEVC,it can be found that after the CTU completed coding in Intra and met the condition of dependencies in Inter,CTU could start the work of encoding of subsequent frames without waiting for the subsequent CTU completing code work in current frame by analyzing the dependence in Intra and Inter.By this way,it could further enhance the degree of parallelism.Also,according to the limited multi-core resources in real coding,paper developed a corresponding resource scheduling strategy which could enhance the utilization of the processing cores and speed up the encoding process.(2)A highly parallel and fast motion estimation scheme is designed.By deeply analyzing two contradictions including the data dependencies and improve degree of parallelism in parallel algorithms for motion estimation Therefore,this thesis used the directed acyclic graph to represent the dependencies between data and utilize its intrusion matrix to update the dependencies after the circular coding process,then the research would go down to the parallel exploration of the PU level in the MER,which is further advanced to improve the parallelism of the motion estimation.As a result,the speedup of parallel encoding could also be improved.(3)A fast parallel Loop filter scheme is designed.It can be analyzed that due to one LCU row delay among the deblocking filtering,prediction processing and SAO,it seriously affects the parallel coding efficiency.Therefore,by means of dividing the LCU could isolate the deblocking filtering and prediction coding,which made the deblocking filter do not need to wait the delay of a LCU row,which accelerated the process of doing with the coded CTU.Meanwhile,SAO could be in process more quickly after the deblock process.This scheme could solve high-latency problem overall and improve coding efficiency.In this thesis,some experiments and related comparative experiments were designed and conducted on multiple cores platform according to the three schemes.In highly parallel Inter/Intra joint WPP coding scheme,its parallel speedup ratio could achieve 9.2 without influencing the coding quality.In highly parallel and fast motion estimation scheme,it improved the degree of parallelism and significantly improves the video coding speed,its parallel speedup ratio could achieve 30.2.In fast parallel Loop filter scheme,it reduced delay between prediction coding and this module,and its the maximum parallel speedup achieved 2.98.From the experimental results,it could be seen that the coding strategy designed in this thesis can not only ensure the video quality,but also improve the parallel coding efficiency. |
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