A Study On Rasterazition And Early Z-Test For Embedded Graphics Processing Units

As an important component of modern computer system, graphics processing systemhas always born massive computing tasks. With the development of3D graphics technolo-gy, graphics processing system within embedded devices faces more and more challenges.The embedded GPU is composed of programmed Shaders and Rasterization system, thelatter mainly in charge of rendering pixels inside basic primitives and the ability of render-ing pixels is one of the most significant performance indicators. For the embedded GPU,there is still some space for the scan-conversion algorithm of rasterization system. Low ren-dering time and power consumption still need to be solved to guarantee the rendering speedand low cost. On the other hand, the embedded GPU needs to access external memory fre-quently, which wastes more bandwith and leads more power consumption, and depth-testoccupies almost a half. Therefore, how to optimize rendering time, power consumptionand memory bandwith has become an important research direction. In this dissertation,some research works focusing on above problems are proposed, including scan-conversionalgorithm of rasterization system, datapath of hardwave optimization, prototype systemverification and bandwith optimized architecture for memory access, to satisfy the needs ofrasterization rendering in embedded GPU.First, an optimized algorithm on traverse during3D rendering for the embedded de-vices is proposed. Two sides are improved based on centerline and tile-scan algorithm,one is for the tile-scan, pre-processing of setup module avoids many logical judgments andthe other is for the pixel-scan, edge detection for each tile processes before pixel-scan toaccelerate the speed of scan-conversion.Second, we propose a hardware architecture of rasterization. Floating design makeshigh precision and pipeline structure design accelerates the rendering speed. We verify theproposed rasterization system in the forms of prototype system based on FPGA, and obtaingood speed and area performance.Finally, an fast and hierarchical Early Z-Test is proposed to reject the pixels which areunnecessary to draw as soon as possible from the tile level and pixel level. Redundant pre-pixel operations including Z reads/writes, color reads/writes and texture reads are avoidedefciently to decrease rendering times. Shared tile cache （TileZcache）with high hitrate cuts down testing cycles and the values of tiles can update dynamically utilizing lesscost. We implement the proposed structure on Attila GPU simulator, contrast performanceindicators with some other algorithms and demonstrate the efectiveness of the results.