Design And Implementation On Rasterization Of Geometric Primitive In Embedded GPU

With the development of computer graphics and the improvement of hardware process, the Graphics Processing Unit has been widely used in variety of embedded devices, such as mobile devices, avionic device and medical equipment. The rasteri-zation of primitive is an important part of GPU.Aiming at the requirement of higher pixel generation speed and lower power consumption in embedded application, this thesis realized an module on the rasteriza-tion of geometric primitive in the fixed pipeline embedded GPU based on Tile Based Rendering by using Verilog HDL. The entire module is divided into front-end and back-end, according to the function of module. The front-end mainly consists of 6 parts:the graphic data reading part receives data by using jumping state machine, the triangular horizontal generation part calculates the endpoints of horizontals by using Bresenham algorithm, the anti-aliasing scanning line generation part uses floating-point arithmetic to calculate the range of the scanning lines, the pre-computation of primitive attributes part using the planar pixel interpolation algo-rithm to calculate incremental interpolation, the point horizontal generation part outputs the endpoints of horizontal directly, the storage of the primitive data of hori-zontal part stores data according to effective signal of horizontal. The back-end mainly consists of 6 parts:the triangular pixel coordinate and attributes calculation part calculates triangular attributes by using circulatory traversal and floating-point arithmetic, the anti-aliasing line pixel coordinate generation part uses circulatory traversal and weighted region anti-aliasing algorithm to calculate pixel coordinates and the weighted value of the anti-aliasing line, the jagged line pixel coordinate gen-eration part uses Bresenham algorithm and segment extend algorithm to calculate pixel coordinates, the segment attribute calculation part uses floating-point arithmetic to calculate pixel attributes of segment, the point pixel generation part uses circula-tory traversal to generate pixel coordinates of the point horizontal, the output data management part uses floating-point arithmetic to process the output pixel attributes.Finally, processing functional simulation of floating-point arithmetic unit, the simulation results show that the arithmetic unit can work correctly. Processing func-tional simulation of the rasterization process of each primitive by using NC-Verilog, the simulation results show that the pixel generation speed of each primitive is 1Pixel/T, which meet design specification. Comparing the images generated by pri-mitive rasterization module and OpenGL, the comparison results show that the mod- ule can draw image properly. Processing the logic synthesis of the entire module be-fore layout by using Design Compiler, under 65 nm CMOS process of the GF, the synthesis results show that the maximum working frequency of the module can reach to 553 MHz, the power of logic unit is 162 mW and the total area of logic unit is 2350432 ?m~2, each meet design specifications.