The Research And Implementation Of Triangle Rasterization Algorithm Based On Tile

The application of modern graphics processing units on embedded devices is very common.With the perfect pursuit of image display quality of mobile devices,the graphics processing system applied to embedded devices also faces greater and greater challenges.The GPU on embedded devices has undergone three major stages of development,from the drawing of fixed pipelines,the drawing of vertex-programmable and pixel-programmable shading pipelines,to the drawing of the final unified shading pipeline.In any of these graphics pipelines,rasterization is always a key part of graphics processing.Simply,rasterization is the process of mapping the basic primitives that carry geometric information to pixel segments on the screen after operations such as scan-conversion,attribute interpolation,and pixel processing.As an important stage of graphics rendering,the speed of rasterization directly determines the overall performance of graphics rendering.For the ever-increasing demand of graphics acceleration performance,how to optimize the rasterization algorithm to effectively improve the graphics acceleration performance of the GPU has become an urgent problem that needs to be studied and solved.The paper takes the triangle rasterization process as the research object,and starts with the triangle rasterization algorithm.Based on the comparative analysis of the advantages and disadvantages of various algorithms,the triangle rasterization algorithm based on Tile is studied in depth.The optimization of algorithm for key problems such as triangle rasterization scanning,attribute interpolation,and anti-aliasing is performed,which speeds up the system's graphics processing capabilities,enhances the efficiency of triangle rasterization,and makes the rasterized image more realistic.Simultaneously,hardware description language is used to complete the hardware design of the algorithm,and a verification platform is built to complete simulation and verification.The main work of the dissertation includes:Firstly,a hierarchical parallel processing scanning algorithm based on Tile is proposed.Based on Zigzag's block scanning algorithm,aiming at the problems existing in the scanning process and combining the ideas of parallelization processing,the algorithm is improved correspondingly.In the process of scanning the pixel blocks along a given scan path,all the pixel blocks covered by the primitive are judged and distinguished,which can be divided into a boundary pixel block at the boundary of the triangle and an internal pixel block completely within the triangle.The further scanning judgment is only made on the pixel block at the boundary of the triangle,which greatly speeds up the efficiency of the scan-conversion.Secondly,the triangular anti-aliasing algorithm has been improved.On the premise of achieving the same anti-aliasing performance,an optimization measure is provided for the problem of large amount of calculation and high hardware resource occupation in the existing multi-sampling anti-aliasing algorithm.Based on the fixed relative position between sub-pixels,an iterative method based on incremental values was proposed to obtain the value of the sub-pixels' edge function.In hardware implementation,16 parallel adders are used for the operation.The optimization algorithm has low computational complexity,low hardware resource occupation,and high drawing efficiency.For triangles of the same size,9806 clocks are consumed when using the existing multi-sampling anti-aliasing algorithm,and 3802 clocks are consumed when using the improved anti-aliasing algorithm of this paper.It saves 6004 clocks and the drawing efficiency is about 2.6 times that of the existing multi-sampling algorithm.Finally,a hardware architecture for triangle rasterization with high parallelism and pipelined processing is established.The multilevel pipelined and parallelized architecture design effectively accelerates the pixel pass rate of graphics rendering.A verification platform is built,and the rasterization unit designed in this paper is simulated to verify the correctness of the module's function and algorithm.The processing speed of the triangle rasterization has been greatly improved in the final: for drawing triangles of the same size,the traditional line scanning algorithm needs 52.97 us,the improved algorithm requires 19.85 us,the scanning time saves about 33 us,and the drawing efficiency increases by 62%.