Research On TSV-aware And Analytical Placement Algorithm For 3D ICs

Integrated circuits(ICs)have become the basis for informationization and intelligence in all walks of life,and they also exist in all aspects of our lives.With the advancement of technology and the development of manufacturing technology,the complexity of modern integrated circuit designs has increased,and the interconnection delay between circuit components has become a bottleneck for circuit performance.In order to overcome this challenge,threedimensional integrated circuits(3D ICs)technology has been extensively studied.3D ICs are circuits that use Through-silicon vias(TSVs)technology to interconnect multi-layer chips in a vertical direction to form a 3D structure,so as to shorten the wirelength in the chip,reduce the chip area,improve chip performance,and increase chip yield.But 3D ICs also bring some significant challenges.Under the current technology,the size of TSVs is larger than that of normal metal wires.Therefore,a large number of TSVs will occupy a large amount of silicon areas,while increasing the final areas and cost of the 3D chip.In the structure of 3D ICs,TSVs are usually placed between macro blocks or standard cells,so the ill-managed TSVs will also reduce routing resources and increase the wirelength in the chip.At present,most works only consider the number of TSVs,because the size of TSVs cannot be ignored in the layout.Therefore,it is very meaningful to consider the sizes and physical locations of the TSVs.Because circuit design itself is an optimization process with a large number of numerical calculations,placement is often a very time-consuming stage.As the size and physical location of TSVs are increased in the layout process,the running time of the algorithm will also increase significantly.This thesis is mainly based on the above two issues,which are the analytical placement algorithm based on TSV and the acceleration of the placement algorithm.For the TSV-based analytical placement problem,this paper proposes a new,analytical,3D layout algorithm.Unlike the previously proposed 3D placement algorithm,the algorithm in this paper is one that can consider the number,size,and physical location of TSVs at the same time.In order to reduce the quality loss of the layout solution,the placement algorithm is a flattening algorithm.The algorithm transforms the placement instance into an electrostatic system.The placement objects(standard cells,macro blocks,and TSVs)are modeled as a positive charge,and the placement density is equivalent to the total potential energy in the system.The algorithm has verified its effectiveness and high performance on two circuits of IBM-PLACE benchmarks and Modern mix-sized benchmarks(MMS).Compared with the leading 3D placement algorithms NTUplace3-3D and e Place-3D,this algorithm can reduce wirelength by 46% and 4% on average on all IBM-PLACE benchmarks.For the problem of placement acceleration,this paper proposes a framework for 3D layout acceleration based on deep learning.By analyzing the similarity between 3D layout algorithm and neural network training,the paper compares the net in the circuit design to the feature vector input in the neural network,compare the coordinates of the module to the weight,and set the label to 0.Using the deep learning framework,a one-to-one correspondence with the neural network training process can be used for placement acceleration.For placement acceleration work,the framework is tested on IBM-PLACE benchmarks.The 3D layout framework allows the TSV-based 3D layout algorithm to shorten the running time of the original algorithm by 3.96 times in all the circuits.