New Topology Of Noc Research

With the development of semiconductor process technology and IC design capacity, the size of the SoC Chip is growing larger and larger, which brings a lot of problems, such as poor scalability, inefficient communication, and the problems of interconnection, clock and power. In order to resolve these problems, Network on Chip (NoC) is proposed in recent years, and has a rapid development in universities and research institutions all over the world.A new NoC topology-Multi Layer Router (MLR) is proposed in this paper, which take both the network performance and hard cost into consideration. Considering the static meterics parameters, such as link number and the network diameter, MLR is compared with the 2D-mesh architecture.The result shows that the link number and the network diameter of MLR are significantly smaller than 2D-mesh. In particular, when the size of the network extend, the advantages of MLR becomes more obvious.When the number of IP core reach 64, the network diameter of MLR can reduce 40% to 2D-mesh.In order to evaluate the dynamic performance of MLR, a software simulation environment is developed based on Network Simulation-2 (NS-2),and the model of the NoC topology is built. The performance improvements of MLR, such as drop rate, latency and throughput have been verified based on the simulations of the MLR architecture and other topologies such as 2D-mesh, wk-recusive and cluster-mesh.The hardware simulation platform of MLR is also implemented, which contains the design of a 16 bit RISC processor named as Mcore. The Mcore is used as an example of IP core in the network which comunicates with its neighbor by the shared Router. The MLR based router is also implemented in Verilog HDL. All the modules and the system have been simulated and verified. On one hand, through the comparison of area and power with 2D-mesh, MLR could save at least 20% hardware cost and 40% dynamic Power. On the other hand, through the implement of the hardward simulation platform, the feasibility of MLR architecture is verified.