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Study On The Measurement And Finite Element Simulation Of Power Electronic Package

Posted on:2014-02-26Degree:MasterType:Thesis
Country:ChinaCandidate:H WuFull Text:PDF
GTID:2248330392961138Subject:Materials engineering
Abstract/Summary:PDF Full Text Request
Power semiconductor devices have made impressive progress,particularly in the increasing capability of handling high current andvoltage, which result in the excess junction temperature and relatedreliability problems due to the increasing power dissipation. It is of vitalimportance that the junction temperature can be kept within a certain limitaccording to the thermal design based on the external cooling conditionand thermal resistance of device package. Hence, thermal resistance ofpackage is a critical thermal parameter both for vendors and customers.This paper summarizes the related standards and methods for thermalresistance measurement. We focused on the junction to case thermalresistance measurement and junction to ambient thermal resistance fordifferent kinds of packages. At the same time, we studied the thermalresistance simulation for power electronic package by finite elementmethod.On the one hand, a thermal resistance tester called T3ster, which isbased on the principle of JESD51-14, is used to measure the junction tocase thermal resistance of three different packages in this paper. Althoughthe principle and method seems perfect theoretically, there exist someuncertainties that affect the accuracy and repeatability of the measurementresults. It also makes request for experienced technician to perform themeasurement. Moreover, we build up a thermal test system based on thestandard of JESD51-1,51-2to measure the junction to ambient thermalresistance of the same packages. It can be seen from the results that thesystem is fairly reliable.On the other hand, finite element analysis by Ansys Workbench iscarried out to model the TO3P package and do thermal simulation. Afterverifying the correctness of the simulation value of thermal resistance bymaking comparison with the datasheet value, the method is used toinvestigate the effect of package materials, dimensions, defects and boundary conditions on thermal resistance. In terms of reducing thethermal resistance, it shows that TO3P package is more preferable forpackaging larger chips. The load and boundary conditions for themeasurement have few effects on the result. The material of solder layerwith higher thermal conductivity is more preferential than that of mouldcompound. The thickness of solder layer should be reduced to the full andthe large voids and corner voids should be particularly concerned duringthe examination of solder layer quality.
Keywords/Search Tags:power device, thermal resistance of package, junctiontemperature, finite element simulation of thermalresistance, thermal resistance measurement
PDF Full Text Request
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