Physical Design Of The Authentication Chip Based On RSA Algorithm For Electronic Systems

Nowadays, the phenomenon of illegal copying and counterfeiting is veryrampant in electronic industry. In order to protect the electronic products fromillegal cloning and copying, a system authentication chip using the ASIC-basedhardware encryption technology is designed. The system authentication chip isembedded in the electronic systems. The host communicates with the authenticationchip in the way of ciphertext. Only when the host receives the correct feedback fromthe authentication chip, the system will work properly.The1024-bit RSA decryption algorithm is applied in the electronic systemauthentication chip which can meet the security requirement. The hostcommunicates with the chip through the I2C bus which has good compatibility withinterfaces and the fewest interface signal lines. So the system authentication chipcan be widely used in many occasions such as digital set-top boxes, IC smart cards,etc..After logic synthesis and DFT design, the gate-level netlist of the electronicsystem authentication chip is exported. Based on SMIC0.18μm CMOS process, thelayout design is present in Cadence SoC Encounter platform to achieve the areaoptimization, timing closure and meet the requirements of power consumption. First,the chip is pre-designed with75%utilization, accroding to the process of floorplan,placement, clock tree synthesis, detailed route and so on. The power planning of thepre-design is carried out roughly, in which only the core ring with the width of10μmis designed. By analyzing the routing congestion, timing and power consumption ofthe pre-design, the results show that the routing congestion of the authenticationchip is not serious, the timing is closure, the power consumption estimated is121.46mW, but there are IR drop and electromigration violations in the pre-design.According to the analysis results, the chip’s utilization is increased to80%, so thearea is reduced by0.09mm2compared with the pre-design. The detailed powerplanning is designed to fix the pre-existing IR drop and electromigration violations.The width of core ring is increased to17μm and the double-layer structure isadopted. Seven pairs of vertical power stripes and three pairs of horizon power stripes are placed in the core area, therefore the requirements of power consumptionare met finally. The timing-driven flow is adopted during the entire layout design.The static timing analysis is performed in each stage of the layout design to meet thetiming closure requirements.After the layout design, the electronic system authentication chip has passed thephysical verification which includes DRC, antenna rule checking, ERC and LVSusing Calibre. Finally the GDSII file is exported. In addition, the chip has passed thelogic equivalence checking using Formality to ensure correctness of the logicfunction.The physical design of the electronic system authentication chip based on RSAalgorithm has been achieved successfully. The final design has met the timingclosure, power consumption and manufacture requirements. The clock frequency is44MHz, the chip area is about3.53mm2, and the power consumption is121.87mW.