Research On High Efficiency Power Amplifier

Wireless communication system is developing towards high efficiency high speed and low power consumption.As the most power consuming module in the wireless communication system, high efficient power amplifier is inevitable.Traditional high efficiency power amplifier mostly made trade-off between linearity and efficiency.By made that trade-off,this thesis designed a Class-AB power amplifier for UWB system, completed chip design by using the TSMC0.13um RF CMOS process.This power amplifier achieves a peak PAE36%,and a20dBm OIP3(output third interception point).Besides,the peak output power of this PA is10dBm.Recently new high linearity high efficiency power amplifier structure has been published.This paper analyzes the advantages and disadvantages of the harmonic enhancement, Doherty and Polar power amplifier.At last this thesis takes Polar structure for the PA using in the WLAN system because of its high linearity and efficiency, as well as because it keeps signal on the amplitude,and this chip design is also completed in0.13um TSMC RF process. This paper designed a high frequency limiter and envelope detector, used to separate signal on AM and PM.,and designed a third order harmonic peaks CLASS-F switching PA.This switching PA achieves a32.5%peak PAE,and a8.5dBm OIP3.Finally the envelope are modulated to the output through the closed loop.And that makes the PAE down to32%,but the OIP3up to14.5dB,increase about6dB.Besides, the peak output power of this PA is18dBm.