CMOS RF Receiver Design For WLAN Applications

The rapidly growing wireless communication market creates a high demand for radio frequency (RF) transceivers. Low cost, low power and small form fact are the essential requirements for modern RF receivers. To accomplish a successful design meeting all these requirements, not only advanced process technology and circuit design techniques are vital, but also a breakthrough on system level, both the system level design methodology and receiver architecture, is necessary.In this dissertation, system level design techniques are explore to generate optimized RF system design starting from wireless communication standards. We propose a method to rationally distribute system specifications among the building blocks of a RF receiver. A CMOS receiver for wireless LAN application is designed to demonstrate the methodology. The receiver is implemented with a low cost, main stream 0.18um CMOS technology. The entire system includes the RF front end and baseband blocks. The simulation results demonstrate its sensitivity is up to -80dBm, noise figure is down to 6.6dB and IIP3 is -16.5dBm.As part of WiFi receiver design, the low noise amplifier (LNA) and mixer have been designed which are working at 2.4GHz.In chapter 3, based on the discussion of input matching and noise performance, a source degeneration structure is used. The simulation results are shown at last. The circuit works at 2.4GHz and achieves 17dB gain, 1.7dB noise figure (NF) and–0.6dBm IIP3-point. The power consumption is only 8mw, from the 1V power supply.In chapter 4, the basic theory of mixer together with the structure is introduced firstly. A double-balanced Gilbert structure with current injection is used according to the analysis of mixer noise and gain. Then, the simulation results are shown.