Research And Design Of The Digital Baseband Of UHF RFID Reader Based On FPGA

Radio Frequency Identification technology is an automatic identification technology ofwireless communication with a non-contact operation, strong ability to identify, long life andother technical advantages that traditional recognition technology cannot go beyond, RFIDreceives widespread attention in the world. Especially the identification technology in UHFfrequency segment has characteristics of far identify distance, fast identify speed, stronganti-interference ability and penetration, etc. which make it a hotspot of current research inthe field of high-tech. Currently, the application of UHF RFID technology covers all areas ofmodern logistics, e-commerce, traffic management of the national economy, has a profoundimpact on improve the efficiency of the industry and enhance the level of information society.UHF RFID Reader is the key equipment in the whole UHF RFID system, the readerdigital baseband section is the core of the reader. The level of performance of the digitalbaseband has a direct impact on the performance of RFID reader. Therefore, research anddesign a high performance digital baseband is very important to improve the performance ofthe reader.In this thesis, on basis of in-depth analyzed and studied on UHF RFID communicationprotocol ISO18000-6C and consulted a large number of relevant literatures at domestic andoverseas, the UHF RFID reader digital baseband section with up to the protocol standard andhigh performance was designed. Details are as follows: firstly, analyzed of current researchfrom three aspects of protocol standards, system development and technical application,focused on the ISO18000-6C protocol provisions and technical requirements for digitalbaseband reader. Secondly, the general framework for the digital baseband section and thecomposition of transmit module, receive module and control module were designed on thebasis of above work, and used Verilog-HDL language to complete the hardware design ofeach module, during the design, CRC generation and checking module was take the parallelCRC algorithm to replace the traditional serial algorithm, increased the data communicationrate; replaced the multiplier with serial structure distributed algorithms based on the separatedlook-up-table to comply filtering function, reduced resource consumption; the control modulewas implemented by Nios II embedded processor, made a reasonable choice betweenhardware cost and system speed, improved system performance. Thirdly, the programs werecompiled, synthesized and simulated by using Quartus II. Finally, the correctness ofcommunication link was verified on the built test platform, and given the simulation andverification results.A modular design was used in the thesis, reduced the complexity of system design, easyto edit, modify and debug; Using hardware description language to design reflects the circuit "hardware soften" design ideas, improved the flexibility in circuit design; Exerting the FPGAdevice superiority of highly integrated and flexible programming, reduced the developmentcosts and enhanced the performance of digital baseband. Experimental results show that, eachmodule designed in this paper can up to protocol standards and has a good performance oncommunication link, achieves the expected target.