Research On Total Ionizing Dose Radiation Effects And Hardening Technique Of Back-Gate For SOI Devices

In the advanced CMOS ICs process, Silicon-on-Insulator (SOI) technology hasextraordinary advantage compared with traditional bulk-silicon technology, such ashigh speed, low power and high integration density. The latch-up of bulk-silicondevice can be eliminated drastically due to the complete dielectric isolation of SOItransistor. In addition, the presence of buried oxide (BOX) can restrict the chargecollection volume and improve the immunity of integrated circuits against theSingle-Event Upset (SEU) and latch-up effectively. However, the total ionizing dose(TID) irradiation responses of SOI transistors are more complex than bulk-silicondevices. Because irradiation-induced charge trapped in the SOI buried oxide andShallow Trench Isolation (STI) can also affect the performance of SOI device.Therefore, give a systematic research for TID effects of SOI devices and explore amethod for radiation hardening is necessary.The work in this thesis focuses on the TID effects of0.2μm Partially-Depleted(PD) SOI device. Then, we discussed the radiation hardening process with Si ionimplantation method for SOI wafer and used the Pseudo-MOS technique for thecharacterization of electrical properties before and after irradiation. The content andmain conclusions are as follows:(1) The TID effects of0.2μm PD SOI device under ON, OFF and TG biasconditions have been investigated. The results show that both front gate and the backgate of device, ON bias is the worst bias condition. Furthermore, we also studied thechanges of Id-Vgcurve for the short channel and narrow channel SOI devices with theincrease of the total radiation dose. The experimental results show that theperformance degradation of the short channel and narrow channel transistors wasserious with the increase of total radiation dose, especially the leakage currentincreased significantly. We analyzed the results of the experiments and thought theradiation induce positive charge trapped in STI wall was the main cause ofperformance degradation.(2) The process of Pseudo-MOS sample preparation and the principle of thePseudo-MOS test were introduced. Then, we also discussed all aspects of thePseudo-MOS test parameters in detail.(3) Three kinds of hardened process for buried oxide layer have beeninvestigated, namely direct Si ion implantation, multiple implantation and multiple anneal, bonding implantation. The results show that the Si ion implantationtechnology can effectively enhance the total dose radiation resistance of SOI material.Si ions are implanted into the buried oxide to form Si nanocrystals, thus creating deepelectron traps with a large capture cross section. The electrons are trapped by theelectron traps, which decreases the influence of the radiation-induced positive chargestrapped in the buried oxide. The modified process of multiple implantation andmultiple anneal can maintain the lattice perfection, making up the lack of direct Si ionimplantation technology. Meanwhile, compared with the bonding implantation, themultiple implantation and multiple anneal process also saved time and money onoverhead.