Design And Research On Image Scaling Engine For Flat Panel Displayer

Scaler chip is necessary in FPD solution system, because it translates the input images, which have different resolution to the fixed resolution image, then displays on LCD Panel. Based on the research of FPD's theory and the analysis of scaler's significance in FPD system, this dissertation presents a front-end design of a Scaler chip and FPGA verification with TOP-Down design topology. The scaler chip can process and generate a wide variety of video graphics formats with programmable scaling rations and timing generation, and translate the input video graphics, which have different resolution to the fixed resolution image, then display clearly and stably on FDP Panel. Furthermore, the scaler can be also integrated to other image processing system as IP core. Scaling engine is the most important part in Scaler system. This dissertation starts with the research of Scaler's system architecture and algorithm, and then VLSI design of Scaler is implemented. Bilinear Interpolation Algorithm and Bicubic Interpolation Algorithm are researched and analyzed, so the best algorithm will be designed to reduce chip cost, improve chip frequency and simplify circuit's redundancy. The transpose FIR Filter is designed to implement horizontal and vertical scaling module, and pipeline structure is used to improve reliability of data processing and reduce chip cost. Scaler established in Bilinear algorithm can scale image on 0.5-4 ratio, and output with XGA mode. Moreover, with limitation of algorithm, distortion of data signal processing and restriction of display in scaler, the quality output image become worse, so that it is necessary for scaler to add picture enhancement module. Picture enhancement includes sharpness, contrast, brightness adjustment, gamma correction and dithering. In the dissertation, the RTL code of Scaler chip is described by using Verilog HDL. In succession, the function verification and logic simulation by VCS, and the implementation with Xilinx ISE 5.2i and FPGA xc2v1000 are presented. Finally, the FPGA verification is presented. Through the logic and function verification, the Scaler proposed to meet the expected performance requirement of the system. When video with different resolution is input into Scaler, video with fixed resolution (XGA) is displayed stably on FPD Panel.