8051IP CORE Design Based On FPGA

This paper completes the design of8051IP CORE, using Verilog hardware description language to design. And Cyclone II FPGA in Altera company through verification. The main research method of CPU integrated design idea and implementation of Core and IP. The paper introduces microcontroller and programmable logic device development process. At the same time, some principles and concepts in the design process of FPGA is also introduced.The51Series MCU this paper designed8051IP Core and Intel have the same instruction set, namely the assembly instructions corresponding to the same machine code. Because the51Series MCU existing development environment is relatively mature, such as Keil, so the design and51series microcontroller compatible instruction set, can use the existing development environment, enhance the use and reduce the workload. The8051IP Core does not contain51Series SCM timer and serial peripherals, but contain external interrupt controller with two levels of priority control. Program memory and data memory is expanded, the practical application can be connected with high-speed memory, such as DDR controller, to improve the CPU instruction and data throughput rate. In the design of the8051IP Core did not follow a machine cycle of51series microcontroller contains12clock cycles. But according to instruction execution stage, a stage corresponds to one clock cycle. This greatly improves the instruction throughput rate.This paper first introduced the technology used and the background, then the MCU and functional characteristics of the development of programmable logic device and8051IP of Core and the basic structure are introduced, and then the detailed design of8051IP Core, then it introduces the related technology of system testing and methods. This paper summarizes the project achievements and improvements.